A parallel (or flash) analog to digital (A/D) converter provides high speed conversion of an analog signal to a digital representation. Previous designs of parallel converters using Josephson junctions attempted to use interferometer periodicity to reduce the number of comparators required for an n-bit A/D converter from 2.sup.n-1 to n. Although such a reduction is desirable from a circuit complexity standpoint, the trade-offs necessary in the interferometer design restrict conversion accuracy and/or high speed performance. Best performance performance could only be achieved with the addition of a sample and hold circuit ahead of the converter.
A second problem with parallel converters is the number of comparators that are required. In a pure parallel converter, for example an 8-bit converter, 255 comparators are required. Such a large number of comparators also requires a complex encoder in order to encode the 255 lines into an eight line output suitable for use or further processing.